Latch is simple, transparent, not clocked, asynchronous, level-sensitive opposed to flip-flop which is edge-triggered, opaque, clocked, synchronous, edge-sensitive.
SR latch as memory element
For instance SR latch can essentially be used to store one bit of information 1:
There are various ways to implement SR latch using gates:
Corresponding concurrent VHDL snippet would be:
library ieee; use ieee.std_logic_1164.all; entity sr_latch is port ( s : in std_logic; r : in std_logic; q : inout std_logic; q_n : inout std_logic); end sr_latch; architecture behavioral of sr_latch is begin q <= r nand q_n; q_n <= s nand q; end behavioral;
Replacing NAND operation with NOR should yield in equivalent circuit with inputs and outputs inverted however such circuit gets stuck in an unstable state. Attempting to simulate such circuit using GHDL results in following error message:
./srlatch_testbench:error: simulation stopped by --stop-delta
This means that GHDL has stopped simulation because states could not settle within --stop-delta=N delta cycles without progressing time.