Gated SR latch

Gated SR latch, also known as clocked SR latch or synchronous SR latch or SR flip-flop can be used as register 1:

Output Inverted Output Set Reset S E R Q Q Enable/Clock

Gated/clocked SR latch

Q Q' S E R

Gated SR latch constructed with four NAND gates

Again corresponding VHDL snippet:

library ieee;
use ieee.std_logic_1164.all;

entity sr_latch is
    port (
        s   : in    std_logic;
        r   : in    std_logic;
        q   : inout std_logic;
        q_n : inout std_logic);
end sr_latch;

architecture behavioral of sr_latch is
begin
    q   <= r nand q_n;
    q_n <= s nand q;
end behavioral;

For instance single SR latch could be implemented using single SN7400N 2 integrated circuit:

http://quarndon.co.uk/images2/components/7400_dil_pin.gif

SN7400N integrated circuit contains four NAND gates

1

http://www.it.kth.se/courses/IL2217/F4_2.pdf

2

http://quarndon.co.uk/index.php?main_page=product_info&products_id=12966

3

http://www.play-hookey.com/digital/sequential/d_nand_latch.html

SR latch latch VHDL KTH