D-latch

Introduction

D latch also known as data latch can be used to trap the value on the output what was set while write enable is high.

D latch internals

D latch is usually composed of an SR latch in conjunction with gating functionality. Mux with output connected to one of the inputs and clock connected to select pin could also be used to model D latch. In several examples write enable is substituted with clock signal so in certain contexts it makes sense to say that D latch is clocked element 3:

Q Q' D E

D latch can be implemented with four NAND gates

Boolean formula corresponding to D latch:

\begin{equation*} Q = E \cdot D + \overline{E} \cdot Q_{previous} \end{equation*}

A 2:1 multiplexer can also be used to implement a latch.

Q D E 2:1

D latch can be implemented with 2:1 mux

Input Enable Output Inverted output D E Q Q

D latch symbol

Corresponding VHDL snippet:

library ieee;
use ieee.std_logic_1164.all;

entity d_latch is
    port (
        clk : in  std_logic;
        d   : in  std_logic;
        q   : out std_logic);
end d_latch;

architecture behavioural of d_latch is
begin
    process(d, clk)
    begin
        if (clk = '1') then
            q <= d;
        end if;
    end process;
end behavioural;

D latch with reset

Reset pin can be added in which case two variations are distinguished, first of them is D latch with asynchronous reset:

process(d, clk, reset)
begin
    if (reset = '0') then
        q <= '0';
    elsif (clk = '1') then
        q <= d;
    end if;
end process;

And another one is with synchronous reset:

process(d, clk, reset)
begin
    if (clk = '1') then
        if (reset = '0') then
            q <= '0';
        else
            q <= d;
        end if;
    end if;
end process;

D-latch states

Possible input/output combinations:

Present state

Next state

State tag

DEQ

DEQ

DEQ

A

000

010

100

B

001

010

101

C

010

000

111

D

011

001

111

E

100

111

000

F

101

111

001

G

110

100

010

H

111

101

010

Flow table:

Present state

Next state (DE)

Output (Q)

00

01

10

11

A

C

E

0

B

C

F

1

C

A

H

0

D

B

H

1

E

A

H

0

F

B

H

1

G

C

E

0

H

C

F

1

Minimized flow table merges rows which have matching next states and matching outputs.

Present state

Next state (DE)

Output (Q)

00

01

10

11

A,C,E,G

A

C

E

H

0

B,D,F,H

B

C

F

H

1

Removing redundant states:

Present state

Next state (DE)

Output (Q)

00

01

10

11

A

A

A

A

B

0

B

B

A

B

B

1

A | 0B | 1D=1E=1D=0E=1D=-E=0D=-E=0

Minimized D latch state diagram

1

http://www.it.kth.se/courses/IL2217/F4_2.pdf

2

http://quarndon.co.uk/index.php?main_page=product_info&products_id=12966

3

http://www.play-hookey.com/digital/sequential/d_nand_latch.html

D latch flip-flop latch SR latch VHDL KTH