Introduction

Flip-flop is edge-triggered, opaque, clocked, synchronous, edge-sensitive opposed to latch which is simple, transparent, not clocked, asynchronous, level-sensitive.

A flip-flop can be constructed from two D latches. Clear distinction is made between rising edge and falling edge triggered flip flops.

Risinge edge triggered flip-flop described using VHDL.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity d_flipflop is
    port (
        clk : in  std_logic;
        d   : in  std_logic;
        q   : out std_logic := '0');
end d_flipflop;

architecture behavioral of d_flipflop is
begin
    process(clk, d)
    begin
        -- Detect rising edge
        if clk'event and clk = '1' then
            q <= d;
        end if;
    end process;
end behavioral;

Critical path

Introducing flip-flops to a circuit makes critical path calculation more complex. At least four cases are distinguished:

• From input to output if no flip-flops are involved.

• Circuit iput to flip-flop input.

• Flip-flop output to circuit output.

• Flip-flop output to flip-flop input within the circuit or to another circuit.

FIFO-s

Flip-flops can be used to construct a synchronous FIFO:

Such FIFO can be modeled using VHDL.

process(clk)
begin
    if (clk='1') and clk'event then
        q(7 downto 0)<= d & q(7 downto 1);
    end if;
end process;

Timing analysis

There are no feedbacks in flip-flop assuming that flip-flop is composed of two D latches, thus delay elements don't have to be introduced to the circuit.

Expressions for the next state:

Excitation table:

Stable states marked in bold are the ones where next state is equal to present state.