Flip-flops

Introduction

Flip-flop is edge-triggered, opaque, clocked, synchronous, edge-sensitive opposed to latch which is simple, transparent, not clocked, asynchronous, level-sensitive.

A flip-flop can be constructed from two D latches. Clear distinction is made between rising edge and falling edge triggered flip flops.

Input Clock Output D E Q Q D E Q Q

Falling edge triggered flip-flop constructed with two D latches.

Input Clock Output D E Q Q D E Q Q

Rising edge triggered flip-flop constructed with two D latches.

Risinge edge triggered flip-flop described using VHDL.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity d_flipflop is
    port (
        clk : in  std_logic;
        d   : in  std_logic;
        q   : out std_logic := '0');
end d_flipflop;

architecture behavioral of d_flipflop is
begin
    process(clk, d)
    begin
        -- Detect rising edge
        if clk'event and clk = '1' then
            q <= d;
        end if;
    end process;
end behavioral;
input clock output

D register symbol

Critical path

Introducing flip-flops to a circuit makes critical path calculation more complex. At least four cases are distinguished:

  • From input to output if no flip-flops are involved.

  • Circuit iput to flip-flop input.

  • Flip-flop output to circuit output.

  • Flip-flop output to flip-flop input within the circuit or to another circuit.

FIFO-s

Flip-flops can be used to construct a synchronous FIFO:

q(4) d clk q(5) q(6) q(7) q(0) q(1) q(2) q(3)

Such FIFO can be modeled using VHDL.

process(clk)
begin
    if (clk='1') and clk'event then
        q(7 downto 0)<= d & q(7 downto 1);
    end if;
end process;

Timing analysis

There are no feedbacks in flip-flop assuming that flip-flop is composed of two D latches, thus delay elements don't have to be introduced to the circuit.

d clk q D E Q Q D E Q Q r

Expressions for the next state:

\begin{equation*} r = clk \cdot d + \overline{clk} \cdot r_{previous} \end{equation*}
\begin{equation*} q = \overline{clk} \cdot r + clk \cdot q_{previous} \end{equation*}

Excitation table:

Present state (rp,qp)

Next state (clk,d)

00

01

10

11

Next state (r,q)

00

00

00

00

10

01

00

00

01

11

10

11

11

00

10

11

11

11

01

11

Stable states marked in bold are the ones where next state is equal to present state.

D latch flip-flop latch critical path SR latch VHDL KTH