Multiplexer or mux for short is essentially a switch. The smallest possible mux has two inputs and one pin for selecting either of two. There are various ways to implement such circuitry.

m d(0) d(1) s

2:1 mux composed of four NAND gates

High level block hides the internal gates.

m d(0) d(1) s 2:1

2:1 mux symbol

Three 2:1 muxes can be combined to form 4:1 mux, in that case one mux is selecting the output of either of two:

m d(0) d(1) d(2) d(3) s(1) s(0) 2:1 2:1 2:1

4:1 mux composed of three 2:1 muxes

High level block for 4:1 hides the internal complexity.

m d(0) d(1) d(2) d(3) s(1) s(0) 4:1

4:1 multiplexer

Muxer can be described in VHDL using case statement in sequential code, also known as clocked body.

library ieee;
use ieee.std_logic_1164.all;

entity mux is
    port (
        a : in  std_logic;
        b : in  std_logic;
        c : in  std_logic;
        d : in  std_logic;
        s : in  std_logic_vector(1 downto 0);
        m : out std_logic);
end mux;

architecture behavioral of mux is
    process(a,b,c,d,s) begin
        case s is
            when "00"   => m <= a;
            when "01"   => m <= b;
            when "10"   => m <= c;
            when others => m <= d;
        end case;
    end process;
end behavioral;

Muxer can be also described in VHDL using with select statement in concurrent code:

architecture behavioral of mux is
    with s select
        m <= a when "00",
        m <= b when "01",
        m <= c when "10",
        m <= d when others;
    end case;
end behavioral;