Processing math: 100%

Lookup table

Introduction

Lookup tables or LUT-s are key component of modern computer hardware.

4-input LUT

Five 4:1 muxes can be combined to form 16:1 mux.

d(0) d(1) d(2) d(3) s(1) s(0) 4:1 4:1 4:1 4:1 4:1 d(4) d(5) d(6) d(7) d(8) d(9) d(10) d(11) d(12) d(13) d(14) d(15) s(2) s(3) m

16:1 mux used in 4-input LUT-s

Those 16 inputs are predefined by FPGA bitstream and in such component is called 4-input LUT-s or 4-LUT for short. The 4 selector inputs essentially address the value.

There are 65536 possible variations for 16-bit cell programming which define the boolean function represented by the 4-LUT. The shorthand notation for the 4-LUT programming is within range:

f0000...fffff

FPGA cell

FPGA cell consists of a lookup table, flip-flop and a bypass mux.

4-LUT 2:1 clk d c b a reset output m

FPGA cell internals

To be precise full adder is also part of the design:

2:1 clk d c b a output m 3-LUT 3-LUT Full Adder carry in 2:1 2:1 carry out reset

Detailed FPGA cell internals

Here the carry chain is explicitly seen.

Boolean function using lookup table #1

Consider following boolean expression:

f(x)=x1¯x2+¯x1x2+x3¯x4

The corresponding truth table:

x(3)

x(2)

x(1)

x(0)

f(x)

0

0

0

0

0

a

0

0

0

1

0

0

0

1

0

1

0

0

1

1

0

0

1

0

0

1

f

0

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

0

0

0

1

f

1

0

0

1

1

1

0

1

0

1

1

0

1

1

1

1

1

0

0

0

4

1

1

0

1

0

1

1

1

0

1

1

1

1

1

0

This boolean expression can be referred to as:

f4ffa(x)

Boolean function using lookup table #2

Consider following boolean expression:

f(x)=x0x1x2x3

The corresponding truth table:

x(3)

x(2)

x(1)

x(0)

f(x)

0

0

0

0

0

6

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

0

1

0

0

1

9

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

0

0

0

1

9

1

0

0

1

0

1

0

1

0

0

1

0

1

1

1

1

1

0

0

0

6

1

1

0

1

1

1

1

1

0

1

1

1

1

1

0

4-LUT function can be referred to as:

f6996(x)
mux VHDL KTH