## Full adder16. Oct '14

Full adder is essentially composed of two half adders.

Full adder can be described in VHDL:

```
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (
a : in std_logic;
b : in std_logic;
ci : in std_logic;
s : out std_logic;
co : out std_logic);
end;
architecture behavioral of full_adder is
begin
s <= a xor b xor ci;
co <= (a and b) or ((a xor b) and ci);
end;
```

Full adder can also be implemented using two 4:1 muxes: